1. Field of the Invention
The present invention relates to a semiconductor device having a circuit constituted by a thin film transistor (hereinafter referred to as a “TFT”) and a manufacturing method of the same. For example, the invention relates to electronic equipment on which an electro-optical device typified by a liquid crystal display panel or a light emitting display device having an organic light-emitting element (or an inorganic light-emitting element) is mounted as a component.
In this specification, ‘semiconductor device’ means any device that can function by utilizing semiconducting properties, and electro-optical devices, semiconductor circuits and electronic equipment are all included in the semiconductor device.
2. Description of the Related Art
In recent years, a technique for forming a thin film transistor (TFT) by using a semiconductor thin film (with a thickness of about several nm to several hundreds of nm) formed over a substrate having an insulating surface has drawn attention. The thin film transistor has been widely applied to electronic equipment such as an IC and an electro-optical device, and developed rapidly, particularly as a switching element for an image display device.
For example, in an active matrix liquid crystal display device, a pixel circuit for performing image display for each functional block, and a driving circuit for controlling the pixel circuit, such as a shift register circuit based on a CMOS circuit, a level shifter circuit, a buffer circuit, and a sampling circuit are formed over one substrate.
It is important to lower the off-current value (a drain current which flows when the TFT is OFF) enough for low power consumption in various circuits.
As a TFT structure to reduce the off-current value, a low concentration drain (LDD: Lightly Doped Drain) structure is known. In this structure, a region in which an impurity element is added at a low concentration is provided between a channel forming region and a source region or a drain region which is formed by adding an impurity element at a high concentration. This region is called an LDD region. Further, as a means for preventing deterioration of the on-current value due to a hot carrier, a structure in which an LDD region is provided so as to overlap the gate electrode with a gate insulating film in between, a so-called GOLD (Gate-drain Overlapped LDD) structure, is known. It is known that by employing such a structure, the high electric field around the drain is eased and hot carrier implantation is prevented, which is effective in preventing the deterioration phenomenon.
In Patent Document 1, a TFT in which LDD regions having different widths are provided with a channel forming region interposed therebetween has been disclosed. The two LDD regions having different widths are formed using a resist mask. Note that the LDD regions do not overlap a gate electrode.
In Patent Document 2, an LDD region which is formed to overlap a gate electrode by doping obliquely with respect to a substrate surface has been disclosed.
In addition, the present applicant has disclosed a TFT manufacturing process in which a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function formed of a diffraction grating pattern or a semi-transparent film is applied in a step of photolithography for forming a gate electrode, in Patent Document 3.    [Patent Document 1] Japanese Patent Laid-Open No. Hei 10-27913    [Patent Document 2] Japanese Patent Laid-Open No. Hei 8-139337    [Patent Document 3] Japanese Patent Laid-Open No. 2002-151523